1. Field
The presently disclosed embodiment pertains to the field of power electronics.
The presently disclosed embodiment pertains more particularly to a method of controlling a three-phase inverter implementing a vector modulation technique.
2. Brief Description of Related Developments
The scientific publication “Optimal Common-Mode Voltage Reduction PWM Technique for Inverter Control With Consideration of the Dead-Time Effects—Part I: Basic Development” (Yen-Shin Lai and Fu-San Shyu—IEEE Transactions on Industry Applications. Vol. 40 No. 6 November/December 2004) is known in the prior art. This scientific publication relates to the PWM (“Pulse Width Modulation”) technique, and more particularly to reducing the common-mode voltage.
U.S. Patent Publication No. US 2014/0070736 (“Bayerische Motoren Werke Aktiengesellschaft”—BMW AG), which describes a power electronics apparatus and a method of piloting for an electrical machine and for the storage of electrical energy is also known in the prior art. This U.S. patent Publication describes a power electronics structure comprising an inverter to which an electrical machine can be connected, and at least one half-bridge to which two electrical energy storage devices can be connected. One of the two electrical energy storage devices supplies at least in a temporary manner the electrical machine and the other of the two electrical energy storage devices charges at least in a temporary manner another electrical energy storage device from among at least the two electrical energy storage devices by means of the electrical machine and of one of the half-bridges. Accordingly, a method of control for switching the power electronics operates according to the principle of spatial vector modulation.
SVM (“Space Vector Modulation”) type modulation is known in the prior art. It is a method implemented in a digital manner to control three-phase inverters. This method is implemented in electric vehicles in particular. Modulation of SVM type uses vectors which correspond to individual switching configurations to generate a reference voltage. FIG. 1 illustrates a three-phase inverter structure. In a binary manner, each vector results from a specific combination. For a three-phase inverter, such as represented in FIG. 1, there are eight (23) possible combinations. Table 1 hereinbelow indicates each vector and the corresponding voltage for each phase on the basis of a switching function which indicates “0” for open (“OFF”) and “1” for closed (“ON”).
TABLE 1Vector corresponding to the switching logicIndexnumberofGate “a”VaoGate “b”VboGate “c”Vcovector0−Vdc/20−Vdc/20−Vdc/200−Vdc/20−Vdc/21Vdc/250−Vdc/21Vdc/20−Vdc/230−Vdc/21Vdc/21Vdc/241Vdc/20−Vdc/20−Vdc/211Vdc/20−Vdc/21Vdc/261Vdc/21Vdc/20−Vdc/221Vdc/21Vdc/21Vdc/27
The SVM method, based as it is on mathematical transformations, is appropriate for programming on processors of “Digital Micro Processors” type.
In traditional SVM methods, the common-mode voltage (CMV) can take the following values: +/−Vdc/2 or +/−Vdc/6 as a function of the vectors used. During the switching times, the common-mode voltage can vary by +/−Vdc/3. The common-mode current or CMC from which the leakage current originates is proportional to the variations of the CMV levels.
Methods for reducing the common-mode voltage have recently been proposed.